This application claims priority from German patent application number 99125461.6 filed Dec. 21, 1999, which is hereby incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a novel multilayer ceramic module structure. More specifically, it relates to the design of multilayer ceramic multichip modules.
2. Description of Related Art
As VLSI circuits become more dense, there is a need in the art to have semiconductor packaging structures that can take full advantage of the density and speed provided by state of the art VLSI devices. Present day modules made of ceramic, typically multilayered ceramic modules, are normally mounted onto cards or boards, with cards or boards combined together to form the central processing unit (CPU) of a computer. The multilayer ceramic (MLC) modules typically have VLSI chips mounted on the top surface.
Multilayer modules are used for the packaging of electronic components, especially integrated circuit chips. Both single chip modules (SCM) and multi chip modules (MCM) are widely used. The most common type of such modules is the multilayer ceramic packaging module. In this type of module the layers consist of a ceramic or glass-ceramic material. However, other types of thickfilm technologies are known, such as glass epoxy and teflon.
The basic technology of multilayer modules was first described by A. J. Blodgett and D. R. Barbour, xe2x80x9cThermal Conduction Module: A High-Performance Multilayer Ceramic Packagexe2x80x9d, IBM Journal of Research and Development 26 (1), pp. 30-36, January 1982, and by A. J. Blodgett, xe2x80x9cMicroelectronic Packagingxe2x80x9d, Scientific American, 249 (1), pp. 86-96, January 1983. The technology of multilayer modules is also described in xe2x80x9cMicroelectronics Packaging Handbookxe2x80x9d, edited by R. R. Tummala and E. J. Rymaszewski, New York, 1988, especially in Chapter 7 entitled xe2x80x9cCeramic Packagingxe2x80x9d, pp. 455-522.
As integrated circuit speeds and packaging densities increase, the importance of the packaging technology becomes increasingly significant. For example, as devices approach gigahertz speed, inductance effects in the package become more significant. Such inductance effects may arise from switching, for example, and are particularly problematic in power and ground leads. Inductance effects in the package can cause ground bounce, signal cross-talk and the like. Increasing circuit size and speed also impact the heat dissipation ability of the package.
Especially VLSI and ULSI chips are designed for high performance applications and are thus limited by noise. The noise is caused by a high number of simultaneously switching off-chip drivers (OCD noise) and by a high number of simultaneously switching latches and the associated logic gates (logic noise). Both noise sources impact and restrict the on-chip and off-chip performance and jeopardize the signal integrity. Both noise sources generate noise due to line-to-line coupling and due to the collapse of the voltage-ground (GND) system. It is known in the art to use on-module capacitors to stabilize the power system. Thereby a major noise reduction is achieved.
A multilayer ceramic fabrication process involves the formation of the green or unfired ceramic layers or sheets, the formation of the conductive paste, the screening of the conductive paste onto the green ceramic sheets and the stacking, laminating and firing of ceramic sheets into the final multilayer ceramic structure. These general processes are known in the art and are, e.g., described in the publication entitled xe2x80x9cA Fabrciation Technique for Multilayer Ceramic Modulexe2x80x9d, H. Kaiser et al, Solid State Technology, May 1972, pp. 5-40 and the U.S. Pat. No. 2,966,719 assigned to Park.
The ceramic green sheet is formed by weighing out the proper portions of the ceramic powder and glass frit, and blending the particles by ball or other milling techniques. The organic binder comprising the thermoplastic resin, plasticizer and solvents is then mixed and blended with the ceramic and glass powders on a ball mill. A slurry or slip is cast into a tape form by extruding or doctor blading. The cast sheet is then allowed to be dried of the solvent constituent in the binder system. After the tape is completely dried, it is then cut into working blanks or sheets; registration holes are formed in the blanks together with the via holes which are selectively punched in the working blanks. The via holes will eventually be filled with a conductive composition to allow for electrical connections from layer to layer in the multilayer ceramics structure.
FIGS. 1a to 1c describe the standard MCM-MLC technology. In FIG. 1a the wiring scheme is described. Between ground (GND) and voltage (V1) mesh planes the signal distribution layers (X, Y), also called xe2x80x9cX/Y wiring areaxe2x80x9d are located. FIG. 1a shows that on a given via pitch the signal and power vias (S, P) are punched through all multilayers of the MCM. The via punch pitch is defined by the manufacturing yield. As an example for today""s MCM-MLC technologies, the via punch pitch is given as 450 xcexcm.
The wiring directions of the two signal distribution layers X, Y are orthogonal to each other in order to minimize vertical coupling. Only one single signal line fits between the vias, therefore this wiring technology is also called 1L/CH (one line per channel) wiring technology.
In FIG. 1b the reference planes for voltage and GND are shown. They are needed to provide the DC current, the AC return current and to shield against vertical coupling from plane pair to plane pair (e.g., X1/Y1 to X2/Y2 to Xn/Yn, wherein X1 . . . Xn and Y1 . . . Yn are successive signal wiring layers).
Finally, FIG. 1c shows the total cross-section of an MCM with all layers. The layer sequence shows 7 fan-out layers (redistribution layers RD1-RD7) on the top embedded in voltage and GND shield layers. The fan-out layers transform the dense chip footprint into a less dense via pattern which starts at the first plane pair (X1, Y1). The redistribution layers are followed by 13 plane pairs (13 PP, X1/Y1, . . . , X13/Y13) of signal wiring layers, which are again embedded in voltage and GND shield layers. The total MCM cross-section thereby consists of 62 layers of ceramic or glass ceramic.
Low-effective inductance (Leff) is crucial for controlling package switching noise levels. The trend for VLSI is to place higher speed circuits at greater densities on a chip. The resultant need for more simultaneous switching mandates a better Leff. Even though Leff will naturally reduce because of the lower on-chip impedances due to the higher circuit counts, it will still be necessary to augment this effect by placing high-frequency decoupling capacitors between associated voltage pins very close to each chip.
However, in view of either the layout of the wiring lines associated with the semiconductor chip or the physical dimensions of the discrete capacitor, the discrete capacitor cannot be positioned such that there is no voltage drop or noise at all.
FIG. 2 shows ground (GND) and voltage (V1) mesh planes and two associated signal wiring layers (X, Y). Also shown are the mesh conductors M1 and M2 on the GND- and the V1-plane, as well as the signal conductors C1 . . . C4, located on signal distribution layer Y. As can be seen from this figure, the width of the mesh-plane (M1, M2) is identical to the width of the signal conductor (C1, C2). Due to an incomplete shielding effect the inductive and capacitive coupling (L/C) between signal conductors C1, C2 and C3, C4 is increased. This holds true also for the coupling between vertical and diagonal neighbors (C3, C4xe2x86x92C1, C2; cf. the arrows in FIG. 2). Thus, this structure generates an unbalanced and asymmetrical coupling at near end and far end.
Thus, there still exists a need in the art to provide a technology for the manufacturing of multilayered ceramic modules having an increased shielding effect as well as superior electrical properties compared to the state of the art structures.
The present invention relates to a method and apparatus to improve coupled noise characteristics and reduce the number of signal layers in a multilayer ceramic module (MCM). Toward this end, preferred embodiments of the present invention provide an increased via punch pitch, thus allowing two wiring channels between adjacent vias. The resultant increase in wirability allows a reduction in the number of signal layers, thereby reducing the total number of layers in the MCM. In addition, the preferred embodiments of the present invention provide voltage and ground mesh plane conductors which are wider than the signal conductors, thereby improving the coupled noise characteristics of the device.
It is therefore an object of the invention to provide a multilayer ceramic structure having superior electrical properties and an increased shielding effect combined with lower manufacturing costs due to reduction of layers.
These and other objects and advantages are achieved by the structure according to the appended claims.